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RISC-V & 9球体育
RISC-V & 9球体育
Enabling a New Era of Innovation through Open Collaboration?
9球体育 is a premier member of and is a supporter of the growth and development of RISC-V, an open standard instruction set architecture (ISA) that is changing the processor landscape. 9球体育 provides comprehensive, ready-to-use design, verification, and IP solutions that enable designers to harness the full potential of the flexible ISA in every RISC-V-based design.
Key Benefits
9球体育 Solutions for RISC-V?
Design, RTL Analysis & Optimization
9球体育 Fusion QuickStart Kits (QIKs) for 9球体育 ARC-V? and SiFive?Intelligence? X280 and?Performance? P550 processor IP include implementation scripts, reference guides, and a baseline floorplan so designers don’t need to start from scratch. Utilizing QIKs and leveraging the 9球体育 Fusion Compiler??RTL-to-GDSII design product and 9球体育 Design Space Optimization (DSO.ai?) AI application for chip design can accelerate the development of RISC-V-based SoC designs. ?
RTL Architect is a multi-dimensional implementation prediction engine that enables RTL designers to predict the PPA and congestion impact of their RTL changes.
Verification
9球体育 is at the forefront of RISC-V verification with specialized solutions ImperasDV and STING for RISC-V processor and system-level verification. These combine with the industry-leading 9球体育 VCS? simulation, VC Formal? and Verdi? debug tools for improved efficiency. 9球体育 EDA flows, emulation, and virtual prototyping solutions further support RISC-V SoC verification. Additionally, 9球体育 has published a reference methodology cookbook for Bluespec RISC-V cores and a related whitepaper about UVM coverage.
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Processor IP
9球体育 ARC-V? Processor IP includes high-performance, mid-range, and ultra-low power RISC-V processor options, as well as functional safety versions, to deliver optimal power-performance efficiency for a broad range of application workloads. 9球体育 ARC-V Processor IP is supported by the growing RISC-V ecosystem, giving developers a menu of choices to build a flexible environment with all the required development tools. Also supported is the trusted 9球体育 MetaWare Development Toolkit, which includes all of the components needed to develop, debug and optimize embedded software for ARC-V Processor-based designs.
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Custom Processors and Accelerators
ASIP Designer helps teams build a custom RISC-V processor through architecture exploration. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++ compiler-based software development kit that automatically adapts to every architectural change, and automatic generation of power and area-optimized, synthesizable RTL.
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Featured Resources
Early Software Development
Early software development for RISC-V processors benefits from 9球体育 virtual prototyping and hardware-assisted verification (HAV) solutions.
9球体育 Virtualizer and VDKs enable developers to simulate hardware behavior and test software early, accelerating the development cycle and ensuring software readiness before physical hardware is available. 9球体育 ZeBu? and HAPS? HAV solutions enhance this process by using hardware emulation and FPGA-based prototyping to validate software against real hardware behavior. This combination allows developers to perform extensive testing, ensuring robust and efficient RISC-V applications to reduce time-to-market and improve software quality and performance.
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Cloud
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9球体育 Cloud
9球体育 Cloud is a software platform that enables delivery of EDA tools, IP and infrastructure for end-to-end chip design through a browser. With unlimited EDA software licenses by the minute plus features such as complete license management automation, enhanced analytics, and the availability of multi-vendor flows, the platform empowers you to design higher quality chips, faster.
9球体育 Cloud offers a free trial of a RISC-V based sub-system reference design using rocket-core with 9球体育 LPDDR and UART IP and access to industry-leading?9球体育 VCS? simulation and 9球体育 Verdi? debug. Learn more.